One particular type of nonvolatile memory cell is the Flash EEPROM (Electrically Erasable Programmable Read-Only Memory). Flash EEPROMs are a type of device which provides electrical erasing. The term "flash" refers to the ability to erase the memory cells simultaneously with electrical pulses. Typically, the erase operation erases the entire memory array (i.e. single transistors are not erased alone).
Known flash EEPROMs are typically programmed by using a cell structure which utilizes a programming voltage of approximately 10 to 15 volts connected to a control gate. These EEPROMs also use a drain voltage of approximately seven to nine volts. Under this operating condition, the conventional flash EEPROM implements a conventional hot carrier injection to raise the threshold voltage of all transistors being programmed.
One problem in the art of EEPROMs is that of over erasing the cell. If a cell is over erased, it will cause false results when aligned bits are read. For example, if a bit of word one is being read and the same bit of word two has been over erased, then current will flow through the transistor for the bit of word two resulting in a logic 0 reading regardless of the logic state of the bit of word one.
Two methods have been used to overcome this problem. The first is the use of an intelligent erase feature. Here, the system measures the total voltage of the array when programed with a logic 0 state (charged). A pulse erasing signal is then applied to the array and the the cells are checked again. This is repeated until none of the cells register a programed response following a pulsed erase signal. However, the problem here is that by the time the last cell is erased, the first cells may be entering an over erased state. This is compensated for by either making the voltage required to trigger the sense amp much higher, giving more room between a zero voltage level and the sense amp level, or requiring a much tighter control over processing so that there is little difference between those cells easily erased and those which require the most pulses. Neither of these options is particularly acceptable.
Another solution to this problem is the use of a series enhancement transistor. This transistor will act as a switch to block the current flow through a bit of a word that is not being accessed. While this helps solve the problem of obtaining erroneous results from over erased bits, it creates other problems of its own. For example, the cells must now be programed and erased using the drain, as opposed to programing with the drain and erasing with the source. Since the ideal conditions for programing and erasing are some what different, this means that a compromise must be reached which would not be ideal for either function.